1. L.Q. Luo , Y.J. Kong , F.X. Deng , X. Qu , Z.Q. Teo , J.Q. Liu , F. Zhang , X.S. Cai , K.M. Tan , K.Y. Lim , P. Khoo , P.Y. Yeo , B.Y. Nguyen , S.M. Jung , S.Y. Siah , D. Shum *, Sr. Member, IEEE GLOBALFOUNDRIES Singapore Pte, Ltd., Singapore, 738406. K.L. Pey , K. Shubhakar, L.Q. Luo Singapore University of Technology and Design, 8 Somapah Road, Singapore, 487372. C.M. Wang , J.C. Xing , G.Y. Liu , Y. Diao , G.M. Lin , F. Luo , L. Tee , V. Markov , S.M. Lemke , P. Ghazavi , N. Do , V. Tiwari , X. Liu , Sr. Member, IEEE Silicon Storage Technology, Inc., A Subsidiary of Microchip Technology Inc., San Jose, CA 95134, U.S.A. 8 th International Memory Workshop Monterey, CA, USA May 2017 40nm Embedded Self - Aligned Split - Gate Flash Technology for High - Density Automotive Microcontrollers

4. performance and reliability are sufficient for meet ing the market demands for next - generation automotive MCUs. For any embedded F lash integration into a logic process , logic device performance must remain unchanged . It is vital to check logic and SRAM devices ’ performance to identify any potential transistor degradation . The final in - line parameters show that , with additional e F lash process, the logic transistor performance and centering are closely match ed to baseline. 32Mb high - d ens ity POR SRAM macros have been included in the development. F ig . 7 show s that the SRAM chip is fully functional at both V max and Vmin with comparable macro yield . The m ajority failure s are SB, indicat ing that the process has no intrinsic issues and show s no major roadblock s to the overall embedded yield. The concept of integrating the F lash modules prior to the logic well has been verifie d . Conclusion In this work we have successfully integrat ed a functional 2.5 V ESF3 Array into a 40nm CMOS logic process with copper and low - K interconnects. This highly modular integration has been verified and match SRAM performance , w hich make s it ideal for potential combinations with mmWave or Analog/power for single chip solutions . High density up to 20Mb product - like automotive array functionality and tight Vt/ current distribution s are demonstrated. SSI p rogramming , poly - to - poly FN e rase , 2.5V read , and under 10ns random read access allow for low - power , high - speed operation, suitable for automotive , general purpose MCU , and smart card markets . Reference s [1] Y.S. Shin et al., VLSI Symp. Tech. Dig.,2005,pp. 156 - 159J . [2] D. Shum et al., IMW, pp.139 - 142, 2012 ; R. Strenz, IEDM 2011, pp. 211 - 214. [3] B.J.Ahn et al., IEEE EDL, vol. 19, pp. 438 - 440, Nov. 1998; S. Kianian et al., Sy mp. VLSl Tech. Dig. , pp.71 - 72 (1994); R. Mih et al, VLSI Symp. Tech. Dig. , 2000, pp. 120 – 121. [ 4 ] Y.H. Wang et al., IEEE TED, vol. 52, pp. 385 - 391, Mar 2005; W.T. Chu et a., IEEE TED, vol 51, pp. 1667 - 1671, Oct 2004 ; Y. Taito et al., ISSCC 2015, pp. 132 - 133 . [ 5 ] N. Akil et al., IEEE TED, vol52,pp. 492 - 499, Apr il 2005 . [6] L.Q. Luo et al., IMW, pp. 165 - 168 , 2016 . [ 7 ] Tkachev, et al., IEEE TED,, vol 59, issue 1, pp.5, 2012. Page | 3

6. SuperFlash ® is a registered trademark of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks mentioned herein are the property of their respective companies. Fig. 5 a) Tight distribution in both on - and off - state Cell read current Ir1 , with good margin to read reference level . Fig. 5b ) Tight erase distribution with good margin to standard user erase condition . Fig.5c) Tight program distribution with good margin to standard user read condition. Fig. 6a 25C Erase V distribution with good margin after cycling. Fig.6b 25C cell read current distribution, with good margin to read reference level . Fig. 6c Erase voltage distribution for 25C cycling vs. 150C cycling. Fig. 6d Read current distribution for 25C cycling vs. 150C cycling. Page | 5

5. Fig ure 2 Schematic cross - section of the ESF3 cell along cell channel (top); TEM cross - section image (bottom). 25ºC 150ºC Fig. 4 Automotive 20Mb Flash Macro Random Read Access Time (tACC) Shmoo Plots with wide temperature range. 8.1ns read demonstrated at worst - case condition . Fig ure 1 Schematics of the ESF3 eFlash process flow ( black: logic; blue: eNVM). FG Oxide FG & ONO Control Gate NVM spacers HV/Tunnel ox WL & EG STI Trench Isolation HV & NVM Wells embedded Array formation Ni silicide Contact Backend of Line (Metal layers) Logic Gate Flash Cell NVM & HV LDD Logic LDD & S/D Figure 3 Die photograph of the 20Mb automotive Flash Macro . WLs BLs Fig. 7 SRAM 32Mb Macro (L: logic+ Flash; R: logic ) shmoo at various VDD & VCS, demonstrated logic functionality and proc ess robustness with additional Flash process . Page | 4

2. 40nm Embedded Self - Aligned Split - Gate Flash Technology for High - Density Automotive Microcontrollers L.Q. Luo, Y.J. Kong, F.X. Deng, X. Qu, Z.Q. Teo, J.Q. Liu, F. Zhang, X.S. Cai, K.M. Tan, K.Y. Lim, P. Khoo, P.Y. Yeo, B.Y. Nguyen, S.M. Jung, S.Y. Siah, D. Shum , Sr. Member, IEEE GLOBALFOUNDRIES Singapore Pte, Ltd., Singapore, 738406. K.L. Pey, K. Shubha kar, L.Q. Luo Singapore University of Technology and Design, 8 Somapah Road, Singapore, 487372. C.M. Wang, J.C. Xing, G.Y. Liu, Y. Diao, G.M. Lin, F. Luo, L. Tee, V. Markov, S.M. Lemke, P. Ghazavi, N. Do, V. Tiwari, X. Liu, Sr. Member, IEEE Silicon Stora ge Technology, Inc., A Subsidiary of Microchip Technology Inc., San Jose, CA 95134, U.S.A. Abstract — This p aper successful ly demonstrates a l ogic - compatible, high performance and high reliab i l ity , automotive - grade 2.5V embedded NVM process extend ing over several generations . A high - density flash macro is used to debug process complexities which arise from the add - on modul es . The modular approach is adopted for integrating self - aligned , floating - gate - based split - gate SuperFlash ® ESF3 cell into 40nm CMOS logic process . Key feature s of the product - like Macro are d ual power supply with input voltage fluctuations , wide operatin g temperature range from - 40 ºC to 150ºC, fast byte / word program under 10 μ s and sector/ chip erase under 10ms. The macro r andom r ead access time is only 8ns under worst case condition s . Key process monitors are characterization and yield of the Macro . E ndurance was extended to 200k cycles and satisfy automotive grade requirement with wide read margin . Post - cycling d at a retention performs very well up to 150 ºC. W afer sort yield is in high dou ble digits , with consistent wafer - to - wafer and within - wafer uniformity, show ing good process control . Th e technology is suitable for high - speed automotive MCU , as well as IoT , smart card , and industrial MCU applications. I ntroduction With the growth of solid - state non - volatile memories (NVM) in storing configuration settings, program code, application parameters and data in consumer , industrial and automotive electronics , demand for embedded NVM is rapidly increasing . The competition in compact product design is driving the embedded F lash memory technology to its scaling limit [1 - 2] . F or automotive applications, robust quality and reliability are required , with zero failure rates at harsh temperature conditions. Code storage requires 10 ns fast random access, 1K endurance, >10 years of retention, while data storage requires 200K endurance, 10 years retention but slower access. Th e ESF3 cell uses highly efficient Source - Side CHE program, poly - to - poly FN tunneling erase, and low - voltage read, with unique advantages in providing over - erase immunity [3]. It offers simple design architecture, high speed and low power operation, good manufacturability and high reliability [4]. It ideally serves the automotive as well as genera l MCU and smart card markets. I t is cru cial to follow the promising scaling path from previous ESF3 generations [ 5 ] . The 40 nm cell size was reported previous ly, characterized using 16Mb Design test Chip ( DTC ) array [6]. In this paper we successfully demonstrate a functionally competitive, l ogic - compatible , automotive - grade embedded process with a high degree of modularity , using 20Mb product - like Flash Macro , together with a 32Mb SRAM macro fabricated on the same silicon , to debug any process complexities that arise from the add - on modules. We present read s hmoo, power consumption, array characteriza tion , and endurance data at 25 ºC and 150 º C . Process Integration The ESF3 memory cell is erased via poly - to - poly FN tunneling across a field - enhanc ed asymmetric tunneling barrier formed between the floating gate ( FG ) and erase gate (EG) [7] and programmed via Source - side CHE Injection through the FG oxide . Compared to other split - gate ( SG ) FG cell concepts which program and erase through the same tunnel dielectric, and charge - trapping cells which rely on hot carrier injection with non - overlapping injection Page | 1

3. points, the ESF3 cell is naturally less susceptible to P/E cycling degradation s . Read voltage is limited to dual power supply ranges, without the need for voltage pumping. This unique combination of operating conditions enables high speed and low power operation required in automotive applications . Fig . 1 show s how the embedded NVM ( F lash memory , High Voltage (HV) peripheral ) modules are integrated into the 40nm logic baseline p rocess flow . Fig . 2 shows the Flash cell structures with a TEM cross - section along the cell channel. A successful embedded NVM process must carefully control the impact of additional process steps (thermal and wet) on baseline logic devices. We choose to integrate NVM process steps before the l ogic m odul e . F irst module after wells formation is the FG oxide through which hot electrons are injected during programming. Next is the F G p oly silicon formation , followed by ONO , C ontrol G ate ( CG ) poly silicon deposit ion, and CG/ONO/FG stack pattern ing . Several dielectric spacers are formed during this process to provide robust isolation between adjacent nodes and to create optimized geometries for enhancing electric fields during erase, program and read. The HV oxide, tunnel oxide, IO gate oxide and core logic gate oxide are formed before deposition of l ogic poly silicon which is shared by logic , IO, c ell WL , cell EG , and HV gates . HV LDD is implanted after the gate is patterned. After this s tep , the whole NVM and HV module are integrated into the logic. The rest of the steps follow a l ogic baseline process. Result s and Discussion Flash Array O perating C ondition summarized in Table 1 . Table 1 ESF3 - 55/40 Erase Program Read Word - Line (WL) 0V ~ 1V Vdd Bit - Line (BL) 0V 1 μA 0.6 - 1 .1 V Coupling Gate (CG) 0V 10.5V Vdd Erase Gate (EG) 12V 4.5V 0V Source - Line (SL) 0V 4.5V 0V Key automotive parameters of the 20Mb Flash Array data match well with previous ly reported chip simulation [6], and have shown high yield consistently in high double digits , with good wafer - to - wafer and within - wafer uniformity, which indicates good process control . Key d esign specs are summarized in Table 2 , with Die photo in Fig . 3. Table 2 ATV Macro Flash Key Specs Silicon data # Memory density 20Mb Sector Size 256 x 38 bits Dual Power Supply 1.1V ± 10%; 2.5V ± 10% Operation Temperature Tj - 40ºC to 150ºC Word Program Time 10 μ s < 10 μ s Read access Time random 10 ns ~ 8 ns Sector Erase Time 10ms < 10ms Chip Erase Time 20ms < 20ms Wake - up time 5 μ s from deep power down pass P/E Endurance ≥ 100K w/o ECC ≥ 200K w/ ECC Pass Data Retention > 10 yrs @125°C Pass # typical condition: Vdd=2.2 5 V~2. 75V ; Vdd11= 0. 99V ~1. 21V ; temperature: - 40 °C ~ 150°C. Fig . 4 shows r andom read access Shmoo plot , demonstrating one of the fastest 40 nm e - NVM chips in the world, with random access time under 8 ns at 25ºC and 8.1 ns at 150ºC. Fig . 4 show s a wide passing window under both Vdd ±10% and Vdd11 ± 10%. Active/Standby Power Consumption s for Automotive 20Mb Flash Macro in Typical Condition (TT at 25 ºC, Vdd11, Vdd 2.5V) are summarized in Tabl e 3 , showing outperform ing performance . Table 3 Category Silicon Data Unit Read 53 μ A/MHz Program 1.8 mA Sector Erase 0.6 mA Standby 285 μ A Deep Power Down 44 μ A Array Characterization Data for 20Mb Automotive Macro at 25 ºC and 150ºC are shown below . Read/ Program/ Erase characteristics are shown in Fig . 5 : Cell read current has tight distribution in both on - and off - state s , with good margin to read reference level ( Fig. 5 a); Erase Voltage has t ight distribution with good margin to standard user erase condition ( Fig. 5 b); and programmed state CGVT has tight distribution with good margin to standard user read condition ( Fig. 5 c). Program Disturb window is sufficient . N o read failures were observed in the 20Mb array after 20 times program FF stress cycles at temperatures up to 150ºC. Fig . 6 shows endurance capability under continuous P/E cycling at 25 ° C and 150 ° C. Endurance Life is capable of ≥ 100K without using error correction, and ≥ 200K using Single Error Correction. Data Retention lifetime is > 10 years @ 125 ° C , as previously reporte d [6] . Overall eFlash Page | 2