1. Optimizing ASIC Designs for SWaP GLOBALFOUNDRIES oday’s aerospace and defense (A&D) systems rely on semicon - ductors that address mission-criti - cal availability, performance, pro - cessing and security requirements, while bal - ancing demands for continuous size, weight and power (SWaP) reduction in each new generation of hardware. The GLOBALFOUNDRIES ® (GF) FX- 14™ ASIC design system merges advanced semiconductor technology with a unique combi - nation of ASIC development methodology, tools, services and GF yield ownership to help A&D companies meet these demands and quickly bring ASICs from concept to production. FX-14 is designed for next-generation com - munications and data center hardware, including digital baseband processing solutions for A&D command and control, radar and global position - ing system applications. To meet the require - ments of these applications, where both SWaP and frequency are crucial, FX-14 utilizes GF’s commercial 14 nm low power FinFET CMOS process technology, 14LPP. SW a P-OPTIMIZED IP AND FEATURES The FX-14 design system includes a library of silicon-proven IP: • Multiple threshold voltage (Vt) FET options for managing power and performance • Standard cell combinatorial gates, flip-flops and latches • Phase-locked loops • 64-bit and 32-bit ARM® processors • A memory compiler that provides multiple embedded memory options (register arrays, register files, ROM, SRAMs and TCAM) • An array of high speed SerDes (HSS) cores, including an advanced 56G offering. The inherent advantages of the 14LPP pro - cess technology and FinFET architecture enable significant SWaP benefits (see Figure 1 ). In ad - dition, the FX-14 library features SWaP-centric elements that enable extensive design flexibility in optimizing solutions for the A&D industry. The embedded memory compiler takes advantage of multiple memory bit cell designs to meet de - sign operational (row address/bit word, single/ multiport), density (die area/size) and frequency requirements. An exceptionally small memory cell can be used to optimize memory density for applications requiring minimal die area, while a performance-tuned memory cell can help maxi - mize memory performance (frequency) for per - formance-driven applications. The variety of I/Os available with FX-14 pro - vides additional SWaP benefits, useful for re - ducing ASIC I/O count, die size and power. I/O choices include: • Three-state bidirectional CMOS I/Os • Low voltage differential signaling (LVDS) I/Os • Multiple HSS cores for both short and long reach communication Reprinted with permission of MICROWAVE JOURNAL ® from the June 2017 Supplement. ©2017 Horizon House Publications, Inc.

2. The GF FX-14 ASIC design sys - tem encompass - es both FX-14 IP and development methodology, re - sulting in GF own - ing manufacturing yield. This further minimizes custom - er development risk. Customers purchase yielded FX-14 modules from GF: modules containing both die and packages that pass GF ASIC man - ufacturing tests. GF’s FX-14 die/ package estima - tion tool estimates both ASIC die con - tent and dimen - sions, including package (module) dimensions, based on customer and GF inputs. The tool affords valuable insights for A&D customers that need to meet specific application SWaP requirements. Additionally, GF development tools for ASIC voltage planning/selection and early ASIC power analy - sis enable early power estimation and trade-off analysis to help minimize power consumption in power-sensitive appli - cations. As part of GF’s extensive commercial semiconductor port - folio, FX-14 builds on 30 years of ASIC expertise, more than a decade of A&D insights gained as a Trusted Foundry supplier and more than 2000 designs released to mask build. The high performance processing, density and power-efficient features of the FX-14 underlying 14LPP technology, combined with an extensive silicon IP portfolio, holistic ASIC methodology ser - vices and vertically integrated supply chain, are designed to enable GF FX-14 A&D customers to quickly develop differenti - ated solutions addressing next-generation challenges. GLOBALFOUNDRIES globalfoundries.com • LPDDR4 PHY • A high band - width memory (HBM) Gen2 PHY, compliant with the JEDEC HBM2 standard and supporting data rates up to 2000 Mbps per data pin. Features such as selective volt - age binning and off-die switched voltage islands pro - vide further oppor - tunities for SWaP reduction. Voltage binning allows the ASIC supply volt - age to be chosen according to the process speed, which is measured during ASIC manufacturing test and re - corded within the die. Voltage islands can be used to power down circuits and IP when not in use. END-TO-END SOLUTION GF pairs FX-14 silicon IP with a vertically integrated and validated ASIC development methodology, optimized through decades of development experience and a strong record of first-time-right designs for a full service ASIC solution (see Figure 2 ). This combination helps optimize customer devel - opment schedules and minimize expense risks. The GF ASIC development methodology utilizes industry- standard design tools and a three-phase netlist signoff pro - cess (release-to-floorplanning, release-to-preliminary and re - lease-to-layout) with highly structured entrance and exit mile - stones. GF is responsible for manufacturing test insertion, ASIC physical design and first-level ASIC package design. GF is also responsible for physical design checking (design rule checking and layout versus schematic), mask build, test gen - eration, wafer manufacturing, ASIC wafer test, package man - ufacturing, die-package bond and assembly (module) and ASIC module test. Additional service options are available, including architecture services and detailed design services. Aerospace and defense ELECTRONICS PRODUCT FEATURE s Fig. 1 FX-14 SWaP benefits compared to GF Cu-32 ASIC process. Results will vary with design. U p to 55% A rea R eduction U p to 50% A ctive P ower R eduction U p to 85% L ess L eakage s Fig. 2 GF offers a vertically integrated, full service ASIC solution. B ackend A ssembly/ T est M anagement P ackaging ( C ontracted) W afer F ab C hip D esign IP D esign